It is common in semiconductor device fabrication to form an epitaxially-deposited silicon junction-receiving layer atop a silicon wafer. The epitaxial layer will have a low concentration of N or P impurities while the substrate is a thicker and higher concentration layer. Any desired type of junction pattern is then formed in the epitaxial layer to form known devices such as MOSFETs, IGBTs, diodes, integrated circuits, and the like.
High voltage semiconductor devices commonly employ a resurf region which is a low concentration region between areas of high potential difference. The resurf region depletes as the voltage difference increases, and is fully depleted before the maximum voltage difference is applied. In the double resurf technique, there are two resurf regions of opposite polarities, both of which deplete as the applied potential difference increases. Such a device and the advantages of using the double resurf technique is detailed in U.S. Pat. No. 4,866,495.
In high voltage devices employing the double resurf technique, the resurf region of one polarity is created by implantation and diffusion of appropriate dopants into an epitaxially grown layer of opposite polarity. The epitaxial region pinched by the diffused resurf region serves as the second resurf region. High breakdown voltage is achieved when the charge in the top (diffused) resurf layer is controlled at approximately 1×1012 cm2 and the charge in the lower (pinched epitaxial) resurf region is controlled at approximately 1.5 to 2×1012 cm2. One outcome of such a construction is that as the depth of the diffused resurf layer varies slightly, the charge in the pinched epi region varies substantially so that control over breakdown voltage is lost. This effect has to be offset by using a thicker epitaxial layer. The thicker epitaxial layer has several drawbacks:                1. Deeper isolation diffusions are needed to electrically isolate different parts of the circuit on an integrated circuit from each other, requiring longer diffusion times at temperatures at or above 1200° C., resulting in lower throughput.        2. Very long diffusion times at 1200° C. or above, causes more defects resulting in lower yield.        3. The long diffusion times at 1200° C. or above also results in a wider isolation diffusion, due to greater lateral diffusion, thus reducing the amount of useful area on a chip.        
U.S. Pat. No. 5,861,657 issued Jan. 19, 1999 to Niraj Ranjan and assigned to the assignee of the present application, proposes an improvement to the above, whereby the thickness of the epitaxial layer is substantially reduced, and the charge distribution is modified. Thus, the majority (greater than about 75% and preferably greater than 80%) of the bottom resurf charge (pinched epi region) is disclosed as contained in the bottom 1 to 4 microns of the epi or in about the bottom 25% or preferably 20% of the epi. The top portion of the epi is much more lightly doped and contains a very small portion of the bottom resurf charge.
The increased charge in the lower epitaxial region is introduced at the beginning of the wafer manufacture process by either of two means:                1. Through implantation of appropriate dopants into the substrate wafers followed by diffusion, prior to epitaxial growth of the lightly doped region.        2. Through an epitaxial growth process in which a thin heavily doped epitaxy is grown first followed by a thicker lightly doped epi growth.        
In the resulting structure, a variation of the depth of the top (diffused) resurf region will have a much smaller effect on the charge contained within the pinched region beneath it. This results in a better control over breakdown voltage with a much thinner epitaxial layer for a given breakdown voltage. The thinner epitaxial layer, in turn, reduces the diffusion processing time needed for forming isolation diffusions and the isolation diffusions have a smaller lateral extent and take up less chip area.